Components

All components are in digsim.circuit.components. They are created with the circuit as their first argument, and an optional name:

from digsim.circuit import Circuit
from digsim.circuit.components import AND

circuit = Circuit()
gate = AND(circuit, "gate", ports=3)

The base class of all components, with the methods they share, is Component.

Inputs

PushButton

PushButton(circuit: Circuit, name: str | None = None)

Bases: CallbackComponent

A push button. Its output is 1 while it is pushed, and 0 otherwise.

Ports

O: Output.

Parameters:

Name	Type	Description	Default
circuit	Circuit	The circuit to add the component to.	required
name	str | None	The component name, the class name if not given.	None

push

push() -> None

Push pushbutton

release

release() -> None

Release pushbutton

OnOffSwitch

OnOffSwitch(circuit: Circuit, name: str | None = None)

Bases: CallbackComponent

A switch that stays on or off. Its output is 1 while it is on.

Ports

O: Output.

Parameters:

Name	Type	Description	Default
circuit	Circuit	The circuit to add the component to.	required
name	str | None	The component name, the class name if not given.	None

turn_on

turn_on() -> None

Turn on the switch

turn_off

turn_off() -> None

Turn off the switch

toggle

toggle() -> None

Toggle the switch

DipSwitch

DipSwitch(
    circuit: Circuit, name: str | None = None, bits: int = 8
)

Bases: CallbackComponent

A row of switches, with one output for each switch.

Ports

0, 1, ...: Outputs, one for each switch, numbered from 0.

Parameters:

Name	Type	Description	Default
circuit	Circuit	The circuit to add the component to.	required
name	str | None	The component name, the class name if not given.	None
bits	int	The number of switches, 2 to 8.	8

bits

bits() -> int

Get number of bits in dipswitch

is_set

is_set(bit: int) -> bool

Test if dip switch bit is set

toggle

toggle() -> None

Toggle the switch

Clock

Clock(
    circuit: Circuit,
    name: str | None = None,
    frequency: int = 1,
)

Bases: CallbackComponent

A clock, its output is a square wave.

Ports

O: Output.

Parameters:

Name	Type	Description	Default
circuit	Circuit	The circuit to add the component to.	required
name	str | None	The component name, the class name if not given.	None
frequency	int	The frequency in Hz.	1

StaticValue

StaticValue(
    circuit: Circuit,
    name: str | None = None,
    width: int = 1,
    value: int = 0,
)

Bases: Component

A constant value on a wire or a bus.

Ports

O: Output, width bits.

Parameters:

Name	Type	Description	Default
circuit	Circuit	The circuit to add the component to.	required
name	str | None	The component name, the class name if not given.	None
width	int	The number of bits, 1 to 16.	1
value	int	The value.	0

VDD

VDD(circuit: Circuit, name: str | None = None)

Bases: Component

A constant logic 1.

Ports

O: Output.

Parameters:

Name	Type	Description	Default
circuit	Circuit	The circuit to add the component to.	required
name	str | None	The component name, the class name if not given.	None

GND

GND(circuit: Circuit, name: str | None = None)

Bases: Component

A constant logic 0.

Ports

O: Output.

Parameters:

Name	Type	Description	Default
circuit	Circuit	The circuit to add the component to.	required
name	str | None	The component name, the class name if not given.	None

Outputs

Led

Led(
    circuit: Circuit,
    name: str | None = None,
    callback: Callable[[Component], None] | None = None,
)

Bases: CallbackComponent

An LED, lit while its input is 1.

Ports

I: Input.

Parameters:

Name	Type	Description	Default
circuit	Circuit	The circuit to add the component to.	required
name	str | None	The component name, the class name if not given.	None
callback	Callable[[Component], None] | None	Called with the component when its input changes.	None

LedBar

LedBar(
    circuit: Circuit,
    name: str | None = None,
    width: int = 8,
)

Bases: CallbackComponent

A row of LEDs showing the bits of a bus.

Ports

I: Input, width bits.

Parameters:

Name	Type	Description	Default
circuit	Circuit	The circuit to add the component to.	required
name	str | None	The component name, the class name if not given.	None
width	int	The number of LEDs, 1 to 16.	8

lit

lit() -> list[bool]

The state of each LED, bit 0 first

HexDigit

HexDigit(
    circuit: Circuit,
    name: str | None = None,
    digits: int = 1,
    dot: bool = True,
)

Bases: CallbackComponent

Hexadecimal digits that show the value of a bus.

Ports

val: Input, 4 bits for each digit. The first digit shows the most significant bits. dot: Input, one bit for each decimal point (only with dot).

Parameters:

Name	Type	Description	Default
circuit	Circuit	The circuit to add the component to.	required
name	str | None	The component name, the class name if not given.	None
digits	int	The number of digits, 1 to 8.	1
dot	bool	Add the decimal point input.	True

get_digits

get_digits() -> int

Get the number of digits

value

value() -> VALUE_TYPE

Get value

dot_active

dot_active(digit_id: int = 0) -> bool

Is the dot active for the selected digit_id?

SevenSegment

SevenSegment(circuit: Circuit, name: str | None = None)

Bases: CallbackComponent

A 7-segment display, with an input for each segment.

Ports

A, B, ..., G: Inputs, one for each segment. dot: Input for the decimal point.

Parameters:

Name	Type	Description	Default
circuit	Circuit	The circuit to add the component to.	required
name	str | None	The component name, the class name if not given.	None

Buzzer

Buzzer(
    circuit: Circuit,
    name: str | None = None,
    tone: str = "A",
)

Bases: CallbackComponent

A buzzer, plays a tone in the GUI while its input is 1.

Ports

I: Input.

Parameters:

Name	Type	Description	Default
circuit	Circuit	The circuit to add the component to.	required
name	str | None	The component name, the class name if not given.	None
tone	str	The note, "A" to "G".	'A'

tone_frequency

tone_frequency() -> float

Get frequency for tone

LogicAnalyzer

LogicAnalyzer(
    circuit: Circuit,
    name: str | None = None,
    sample_rate: int = 100,
)

Bases: CallbackComponent

A logic analyzer, keeps the last 100 samples of each input to show them in the GUI.

Ports

A, B, ..., H: Inputs.

Parameters:

Name	Type	Description	Default
circuit	Circuit	The circuit to add the component to.	required
name	str | None	The component name, the class name if not given.	None
sample_rate	int	The samples per second.	100

Gates

AND

AND(
    circuit: Circuit,
    name: str | None = None,
    ports: int = 2,
)

Bases: ConfigPortsComponent

An AND gate: Y is 1 when all inputs are 1.

Ports

A, B, ...: Inputs, one for each of ports, named from A. Y: Output.

Parameters:

Name	Type	Description	Default
circuit	Circuit	The circuit to add the component to.	required
name	str | None	The component name, the class name if not given.	None
ports	int	The number of inputs, 2 to 8.	2

OR

OR(
    circuit: Circuit,
    name: str | None = None,
    ports: int = 2,
)

Bases: ConfigPortsComponent

An OR gate: Y is 1 when at least one input is 1.

Ports

A, B, ...: Inputs, one for each of ports, named from A. Y: Output.

Parameters:

Name	Type	Description	Default
circuit	Circuit	The circuit to add the component to.	required
name	str | None	The component name, the class name if not given.	None
ports	int	The number of inputs, 2 to 8.	2

NOT

NOT(circuit: Circuit, name: str | None = None)

Bases: Component

A NOT gate: Y is the inverse of A.

Ports

A: Input. Y: Output.

Parameters:

Name	Type	Description	Default
circuit	Circuit	The circuit to add the component to.	required
name	str | None	The component name, the class name if not given.	None

XOR

XOR(
    circuit: Circuit,
    name: str | None = None,
    ports: int = 2,
)

Bases: ConfigPortsComponent

An XOR gate: Y is 1 when an odd number of inputs are 1.

Ports

A, B, ...: Inputs, one for each of ports, named from A. Y: Output.

Parameters:

Name	Type	Description	Default
circuit	Circuit	The circuit to add the component to.	required
name	str | None	The component name, the class name if not given.	None
ports	int	The number of inputs, 2 to 8.	2

XNOR

XNOR(
    circuit: Circuit,
    name: str | None = None,
    ports: int = 2,
)

Bases: ConfigPortsComponent

An XNOR gate: Y is 1 when an even number of inputs are 1.

Ports

A, B, ...: Inputs, one for each of ports, named from A. Y: Output.

Parameters:

Name	Type	Description	Default
circuit	Circuit	The circuit to add the component to.	required
name	str | None	The component name, the class name if not given.	None
ports	int	The number of inputs, 2 to 8.	2

NAND

NAND(
    circuit: Circuit,
    name: str | None = None,
    ports: int = 2,
)

Bases: ConfigPortsComponent

A NAND gate: Y is 0 when all inputs are 1.

Ports

A, B, ...: Inputs, one for each of ports, named from A. Y: Output.

Parameters:

Name	Type	Description	Default
circuit	Circuit	The circuit to add the component to.	required
name	str | None	The component name, the class name if not given.	None
ports	int	The number of inputs, 2 to 8.	2

NOR

NOR(
    circuit: Circuit,
    name: str | None = None,
    ports: int = 2,
)

Bases: ConfigPortsComponent

A NOR gate: Y is 0 when at least one input is 1.

Ports

A, B, ...: Inputs, one for each of ports, named from A. Y: Output.

Parameters:

Name	Type	Description	Default
circuit	Circuit	The circuit to add the component to.	required
name	str | None	The component name, the class name if not given.	None
ports	int	The number of inputs, 2 to 8.	2

MUX

MUX(
    circuit: Circuit,
    name: str | None = None,
    ports: int = 2,
    width: int = 1,
)

Bases: Component

A multiplexer: Y is the input that S selects.

Ports

A, B, ...: Inputs, one for each of ports, width bits. S: Select input, 0 selects A, 1 selects B and so on. Y: Output, width bits.

Parameters:

Name	Type	Description	Default
circuit	Circuit	The circuit to add the component to.	required
name	str | None	The component name, the class name if not given.	None
ports	int	The number of inputs, 2, 4 or 8.	2
width	int	The number of bits of each input.	1

Flip-flops

DFF

DFF(
    circuit: Circuit,
    name: str | None = None,
    async_reset: bool = False,
    clock_enable: bool = False,
    width: int = 1,
)

Bases: Component

A D flip-flop: Q takes the value of D on a rising edge of C.

Ports

D: Data input, width bits. R: Reset input, 1 sets Q to 0 at once (only with async_reset). E: Clock enable input, the clock edge is ignored while it is 0 (only with clock_enable). C: Clock input. Q: Output, width bits.

Parameters:

Name	Type	Description	Default
circuit	Circuit	The circuit to add the component to.	required
name	str | None	The component name, the class name if not given.	None
async_reset	bool	Add the reset input R.	False
clock_enable	bool	Add the clock enable input E.	False
width	int	The number of bits.	1

SR

SR(circuit: Circuit, name: str | None = None)

Bases: MultiComponent

An SR latch built from two NOR gates: S sets Q to 1 and R resets it to 0.

Ports

S: Set input. R: Reset input. Q: Output. nQ: Inverted output.

Parameters:

Name	Type	Description	Default
circuit	Circuit	The circuit to add the component to.	required
name	str | None	The component name, the class name if not given.	None

SRFF

SRFF(circuit: Circuit, name: str | None = None)

Bases: Component

An SR flip-flop: S sets Q to 1 and R resets it to 0, without a clock. R wins when both are 1.

Ports

S: Set input. R: Reset input. Q: Output.

Parameters:

Name	Type	Description	Default
circuit	Circuit	The circuit to add the component to.	required
name	str | None	The component name, the class name if not given.	None

ClockedSRFF

ClockedSRFF(circuit: Circuit, name: str | None = None)

Bases: Component

A clocked SR flip-flop: on a rising clock edge, S sets Q to 1 and R resets it to 0. R wins when both are 1.

Ports

S: Set input. C: Clock input. R: Reset input. Q: Output.

Parameters:

Name	Type	Description	Default
circuit	Circuit	The circuit to add the component to.	required
name	str | None	The component name, the class name if not given.	None

ClockedJKFF

ClockedJKFF(circuit: Circuit, name: str | None = None)

Bases: Component

A JK flip-flop: on a rising clock edge, J sets Q to 1, K resets it to 0, and both toggle it.

Ports

J: Input. C: Clock input. K: Input. Q: Output.

Parameters:

Name	Type	Description	Default
circuit	Circuit	The circuit to add the component to.	required
name	str | None	The component name, the class name if not given.	None

ClockedTFF

ClockedTFF(circuit: Circuit, name: str | None = None)

Bases: Component

A T flip-flop: Q toggles on a rising clock edge while T is 1.

Ports

T: Input. C: Clock input. Q: Output.

Parameters:

Name	Type	Description	Default
circuit	Circuit	The circuit to add the component to.	required
name	str | None	The component name, the class name if not given.	None

FlipFlop

FlipFlop(
    circuit: Circuit,
    name: str | None = None,
    display_name: str | None = None,
)

Bases: Component

Lets the GUI choose a flip-flop type. In Python, create SRFF, ClockedSRFF, ClockedJKFF or ClockedTFF directly.

Parameters:

Name	Type	Description	Default
circuit	Circuit	The circuit to add the component to.	required
name	str | None	The component name, the class name if not given.	None

Buses and labels

Bus2Wires

Bus2Wires(
    circuit: Circuit,
    name: str | None = None,
    width: int = 1,
    enable: list[int] | None = None,
)

Bases: Component

Splits a bus into single-bit wires.

Ports

bus: Input, width bits. bus_0, bus_1, ...: Outputs, one for each enabled bit. bus_0 is the least significant bit.

Parameters:

Name	Type	Description	Default
circuit	Circuit	The circuit to add the component to.	required
name	str | None	The component name, the class name if not given.	None
width	int	The number of bits.	1
enable	list[int] | None	The bits to have outputs for, all if None.	None

Wires2Bus

Wires2Bus(
    circuit: Circuit,
    name: str | None = None,
    width: int = 1,
)

Bases: Component

Merges single-bit wires into a bus.

Ports

bus_0, bus_1, ...: Inputs, one for each bit. bus_0 is the least significant bit. bus: Output, width bits.

Parameters:

Name	Type	Description	Default
circuit	Circuit	The circuit to add the component to.	required
name	str | None	The component name, the class name if not given.	None
width	int	The number of bits.	1

LabelWireIn

LabelWireIn(
    circuit: Circuit,
    name: str | None = None,
    label: str = "",
    width: int = 1,
)

Bases: Component

A Wire Sink: passes its input to every LabelWireOut with the same label, without a drawn wire.

Ports

: Input, named like the label, width bits.

Parameters:

Name	Type	Description	Default
circuit	Circuit	The circuit to add the component to.	required
name	str | None	The component name, the class name if not given.	None
label	str	The label.	''
width	int	The number of bits.	1

label

label() -> str

Return Label

LabelWireOut

LabelWireOut(
    circuit: Circuit,
    name: str | None = None,
    label: str = "",
    width: int = 1,
)

Bases: Component

A Wire Source: outputs the signal of the LabelWireIn with the same label.

Ports

: Output, named like the label.

Parameters:

Name	Type	Description	Default
circuit	Circuit	The circuit to add the component to.	required
name	str | None	The component name, the class name if not given.	None
label	str	The label.	''
width	int	The number of bits, used when there is no LabelWireIn with the label yet.	1

label

label() -> str

Return Label

Verilog and ICs

YosysComponent

YosysComponent(
    circuit: Circuit,
    path: str | Path | None = None,
    name: str | None = None,
)

Bases: MultiComponent

A component built from a Verilog file or a Yosys JSON netlist.

Ports

The ports of the Verilog module, with the same names and widths.

Parameters:

Name	Type	Description	Default
circuit	Circuit	The circuit to add the component to.	required
name	str | None	The component name, the class name if not given.	None
path	str | Path | None	A Verilog file (.v) or Yosys netlist (.json) with one module, or None to create the component later with create_from_netlist().	None

create_from_netlist

create_from_netlist(netlist_object: YosysNetlist) -> None

Create component from netlist object

reload_from_netlist

reload_from_netlist(netlist_object: YosysNetlist) -> None

Reload netlist from netlist object

reload_file

reload_file() -> None

Reload yosys verilog/json-netlist file

IntegratedCircuit

IntegratedCircuit(
    circuit: Circuit,
    name: str = "IC",
    ic_name: str | None = None,
)

Bases: YosysComponent

A classic logic chip, from the Yosys netlists in digsim/circuit/components/ic.

Ports

The ports of the chip.

Parameters:

Name	Type	Description	Default
circuit	Circuit	The circuit to add the component to.	required
name	str	The component name, the class name if not given.	'IC'
ic_name	str | None	The netlist's file name without .json, like "74162" or "7448".	None

Memory

Mem64kByte

Mem64kByte(
    circuit: Circuit,
    rom_filename: str | Path | None = None,
    rom_address: int = 0,
)

Bases: Component

A 64 kB memory, read or written on a rising clock edge. It is always named Memory.

Ports

clk: Clock input. Address: Input, 16 bits. DataIn: Input, 8 bits. WE: Write enable input, 1 writes DataIn, otherwise DataOut is read. DataOut: Output, 8 bits.

Parameters:

Name	Type	Description	Default
circuit	Circuit	The circuit to add the component to.	required
rom_filename	str | Path | None	A binary file loaded into the memory when it is created.	None
rom_address	int	The address to load the file at.	0

MemStdOut

MemStdOut(circuit: Circuit, address: int = 32768)

Bases: Component

Prints the characters written to one address, like a memory-mapped terminal. A newline (0x0A) prints the whole line.

Ports

clk: Clock input. Address: Input, 16 bits. DataIn: Input, 8 bits. WE: Write enable input.

Parameters:

Name	Type	Description	Default
circuit	Circuit	The circuit to add the component to.	required
address	int	The address to print the characters written to.	32768

Other

Note

Note(
    circuit: Circuit,
    name: str | None = None,
    text: str = "",
)

Bases: Component

A text note in the GUI. It has no ports.

Parameters:

Name	Type	Description	Default
circuit	Circuit	The circuit to add the component to.	required
name	str | None	The component name, the class name if not given.	None
text	str	The text.	''