Synthesis

See Verilog and Yosys for how synthesis is used.

Synthesis

Synthesis(
    verilog_files: VerilogFiles, verilog_top_module: str
)

Synthesizes Verilog into a netlist with Yosys, which a YosysComponent can be built from.

Parameters:

Name	Type	Description	Default
verilog_files	VerilogFiles	One Verilog file, or a list of them.	required
verilog_top_module	str	The name of the module to synthesize.	required

list_modules classmethod

list_modules(verilog_files: VerilogFiles) -> list[str]

The names of the modules in Verilog files.

Raises:

Type	Description
SynthesisException	If Yosys reports an error, like a syntax error.

synth_to_json

synth_to_json(silent: bool = False) -> str

Synthesize, and return the netlist as JSON text.

Parameters:

Name	Type	Description	Default
silent	bool	Don't print the Yosys log.	False

Raises:

Type	Description
SynthesisException	If Yosys reports an error, like a syntax error.

synth_to_dict

synth_to_dict(silent: bool = False) -> dict[str, Any]

Synthesize, and return the netlist as a dict, for YosysNetlist(**netlist_dict).

Parameters:

Name	Type	Description	Default
silent	bool	Don't print the Yosys log.	False

Raises:

Type	Description
SynthesisException	If Yosys reports an error, like a syntax error.

synth_to_json_file

synth_to_json_file(
    filename: str | Path, silent: bool = False
) -> None

Synthesize, and write the netlist to a JSON file.

Parameters:

Name	Type	Description	Default
filename	str | Path	The netlist file to write.	required
silent	bool	Don't print the Yosys log.	False

Raises:

Type	Description
SynthesisException	If Yosys reports an error, like a syntax error.

get_log

get_log() -> list[str]

The Yosys log of the last synthesis

SynthesisException

Bases: DigsimException

Yosys could not synthesize the Verilog, the message is the Yosys error