Verilog and Yosys¶
DigSim simulates Verilog designs by first turning them into a netlist, a list of gates and how they are connected. This is done with Yosys, an open-source Verilog synthesis tool.
DigSim ships with YoWASP, a portable WebAssembly build
of Yosys, so nothing extra needs to be installed. If a native yosys is found on your
PATH, it is used instead.
You don't always need to synthesize by hand: the GUI and YosysComponent both accept
.v files and synthesize them on load. Creating a netlist yourself is useful when the
design has several modules, or when the same design is loaded often (synthesis of large
designs takes a while).
The synthesis helper¶
DigSim includes a small command-line helper:
python -m digsim.synth synth -i <file1.v> [<file2.v> ...] -o <netlist.json> -t <top_module>
| Option | Description |
|---|---|
-i, --input-files |
One or more Verilog files |
-o, --output-file |
The JSON netlist to write |
-t, --top |
The name of the top module |
-s, --silent |
Hide the Yosys output |
To list the modules found in a set of Verilog files:
python -m digsim.synth list -i <file1.v> [<file2.v> ...]
Synthesis from Python¶
from digsim.synth import Synthesis
synthesis = Synthesis(["counter.v"], "counter")
synthesis.synth_to_json_file("counter.json")
synth_to_dict() returns the netlist instead of writing it, see
testbenches.
Running Yosys directly¶
Yosys is also available as the yowasp-yosys command. Start it interactively:
yowasp-yosys
The following script is what DigSim itself uses, and gives good results:
read -sv <verilog_file.v>
hierarchy -top <top_module>
proc; flatten
memory_dff
proc; opt; techmap; opt
synth -noabc -top <top_module>
write_json <netlist.json>
Save the commands in a file to run them as a script:
yowasp-yosys <script.ys>
Limitations¶
- A Verilog file loaded directly into a Yosys component can contain only one module. Synthesize multi-module designs into a netlist first.
- When reloading a component, its ports must keep the same names and widths.
See the Yosys documentation for everything else Yosys can do.